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<div class="header">
  <div class="headertitle"><div class="title">SDMMC_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Secure digital input/output Interface.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:ab241f9bc57b5606c7cdad92a94130b5e" id="r_ab241f9bc57b5606c7cdad92a94130b5e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ab241f9bc57b5606c7cdad92a94130b5e">POWER</a></td></tr>
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</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Secure digital input/output Interface. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a2b4dfe4d760d0522d58f64e409c0dd3b" name="a2b4dfe4d760d0522d58f64e409c0dd3b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a2b4dfe4d760d0522d58f64e409c0dd3b">&#9670;&#160;</a></span>ACKTIME</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::ACKTIME</td>
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<p>SDMMC Acknowledgement timer register, Address offset: 0x40 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa4a8ca4a55a6c1b0d2837bb1490efea6">&#9670;&#160;</a></span>ARG</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::ARG</td>
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<p>SDMMC argument register, Address offset: 0x08 </p>

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<a id="ac432d7f247e2f199f387a9d81a70dbe3" name="ac432d7f247e2f199f387a9d81a70dbe3"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac432d7f247e2f199f387a9d81a70dbe3">&#9670;&#160;</a></span>CLKCR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::CLKCR</td>
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<p>SDMMC clock control register, Address offset: 0x04 </p>

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<a id="ad67342999b4fb5e7c7249935ea96d02f" name="ad67342999b4fb5e7c7249935ea96d02f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ad67342999b4fb5e7c7249935ea96d02f">&#9670;&#160;</a></span>CMD</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::CMD</td>
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<p>SDMMC command register, Address offset: 0x0C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8f6c92b986930f9f8a9f9ec3b557bb9a">&#9670;&#160;</a></span>DCOUNT</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t SDMMC_TypeDef::DCOUNT</td>
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<p>SDMMC data counter register, Address offset: 0x30 </p>

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<a id="aa179173b3d0e158365b13f9ccdad1665" name="aa179173b3d0e158365b13f9ccdad1665"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aa179173b3d0e158365b13f9ccdad1665">&#9670;&#160;</a></span>DCTRL</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::DCTRL</td>
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<p>SDMMC data control register, Address offset: 0x2C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4e2ca4e135c5074163d108bea39330fc">&#9670;&#160;</a></span>DLEN</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::DLEN</td>
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<p>SDMMC data length register, Address offset: 0x28 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#abce8a3725f3ea302da79e28f75ed8e5f">&#9670;&#160;</a></span>DTIMER</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SDMMC_TypeDef::DTIMER</td>
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<p>SDMMC data timer register, Address offset: 0x24 </p>

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<p>SDMMC data FIFO register, Address offset: 0x80 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a99775edb5f62c67e26fa0aa00293d51c">&#9670;&#160;</a></span>ICR</h2>

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<p>SDMMC interrupt clear register, Address offset: 0x38 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a18154fe330935603948726c1fb81ce8c">&#9670;&#160;</a></span>IDMABASE0</h2>

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<p>SDMMC DMA buffer 0 base address register, Address offset: 0x58 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a316749d0797c2d4525a3b5ba5a2dd205">&#9670;&#160;</a></span>IDMABASE1</h2>

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<p>SDMMC DMA buffer 1 base address register, Address offset: 0x5C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af0af1ac79c77322f6eed777232479dd9">&#9670;&#160;</a></span>IDMABSIZE</h2>

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<p>SDMMC DMA buffer size register, Address offset: 0x54 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a60742096500a81513c2331f206dcb8dc">&#9670;&#160;</a></span>IDMACTRL</h2>

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<p>SDMMC DMA control register, Address offset: 0x50 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9a46a6f18da82b5ad11b8566b1cf0dfe">&#9670;&#160;</a></span>IPVR</h2>

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<p>SDMMC data FIFO register, Address offset: 0x3FC </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a8f40e43afa9cf4ecf21c0cd1b2650560">&#9670;&#160;</a></span>MASK</h2>

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<p>SDMMC mask register, Address offset: 0x3C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ab241f9bc57b5606c7cdad92a94130b5e">&#9670;&#160;</a></span>POWER</h2>

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<p>SDMMC power control register, Address offset: 0x00 </p>

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<p>Reserved, 0x44 - 0x4C - 0x4C </p>

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<p>Reserved, 0x60-0x7C </p>

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<p>Reserved, 0x84-0x3F8 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aca71c167ec5fbe3884109e0bd3fb51fb">&#9670;&#160;</a></span>RESP1</h2>

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<p>SDMMC response 1 register, Address offset: 0x14 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a3f1ab9eeca1d08e5fc50b6a8a0ee0257">&#9670;&#160;</a></span>RESP2</h2>

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<p>SDMMC response 2 register, Address offset: 0x18 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae4a9250b0100c1a251354d64dde42300">&#9670;&#160;</a></span>RESP3</h2>

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<p>SDMMC response 3 register, Address offset: 0x1C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aebd8ffdd133537059f29fd5fecd6e290">&#9670;&#160;</a></span>RESP4</h2>

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<p>SDMMC response 4 register, Address offset: 0x20 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a33c78086429a7eed4d57a5633a9d78f2">&#9670;&#160;</a></span>RESPCMD</h2>

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<p>SDMMC command response register, Address offset: 0x10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a9bbd3a78b1a7fb30c53e1d17a31b9b32">&#9670;&#160;</a></span>STA</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#af63697ed9952cc71e1225efe205f6cd3">__I</a> uint32_t SDMMC_TypeDef::STA</td>
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<p>SDMMC status register, Address offset: 0x34 </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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